1. Technical Field
The present invention relates generally to differential data latch systems and more specifically to achieving higher sensitivity and higher speed in such systems.
2. Background Art
Differential data latch systems have been used in digital circuits that require a sample-and-hold of a data stream so that subsequent circuits can perform digital functions such as synchronization, delay, multiplex/demultiplex, frequency division, and other digital signal processing (DSP) operations, which are essential to modern electronic systems.
When conventional latch systems are used to sample a fast data stream, they must sample and hold data within a fraction of the data bit-width, which is the duration of two adjacent high-to-low and low-to-high transitions when the data is at its highest rate. The minimum times required for the conventional latch systems to sample and hold the data are referred to as the setup and hold times, respectively.
More specifically, the setup time is the minimum amount of time required for the conventional latch system to sample the data signal after the data is switched to a new state in a sample mode and to produce a sufficient amount of signal to successfully hold the sampled data in a subsequent hold mode. The setup time is defined as the amount of time between the mid-point of the data transition and the mid-point of the clock transition. The sample and hold modes are switched by the transitions of a clock.
The hold time refers to the minimum amount of time required for the conventional latch system to hold the sampled data after the clock transition to the hold mode and before the conventional latch system is switched to a different state. Like the setup time, it is also defined as the amount of time between the mid-point of the clock and the mid-point of the data transition, but in this case, the time indicates the time required for correct operation after a clock transition instead of before a clock transition.
The hold time represents the minimum amount of time the data signal must maintain a sufficient amount of voltage after the clock transition to the hold mode in order for data regeneration to occur so the data will be held. In order for data regeneration to occur, the output voltage must reach a certain level. If the clock and data stream are too fast, the difference of the transition times could be less than the minimum required hold time for successful operation of the conventional latch system and the output voltage will not have time to reach the desired level for data regeneration and the conventional latch system will lose the data in the hold mode.
A major problem occurs when the speed of operation of the conventional latch systems increases. Because the setup and hold times represent the minimum time necessary for successful operation, they are the limiting factors when increasing the speed of the clock and data stream.
The above is a particularly serious problem when the conventional latch systems are used in multiple-phase data demultiplexer systems. In these demultiplexer systems, a number of differential latch systems are connected to clocks, which are offset in phase from each other. They share a single serial data stream, which requires demultiplexing. The data stream does not cause a problem in the conventional latch systems when two consecutive bits in the serial data stream are at the same state.
However, when the next bit in the serial data stream is in an opposite state from the prior bit, there is a significant amount of disturbance in the voltage. Unfortunately, this disturbance reduces the amount of voltage available for regeneration and causes the conventional latch system to not be able to hold the data, thus limits the ability of the conventional latch system to operate at higher speeds.
Thus, to increase the speed of the clock and data stream in multiple-phase demultiplexer system, the hold time must be extended when there are opposite consecutive switching bits in the data stream.
Another major problem with the conventional latch system is its lack of sensitivity. Lack of sensitivity is defined as requiring a higher input voltage in order to operate. This is an issue because in actual operating conditions, the amplitude of incoming data bits can be very low due to attenuation caused by external transmission media, such as transmission lines and systems. If the amplitude of the incoming data bit is too low, data regeneration cannot occur and the conventional latch system loses the previously sampled data. This leads to errors in data transmission. Because the integrity of data can depend on the sensitivity, increasing the sensitivity of differential latch systems is imperative.
Solutions to these problems have long been sought but have long eluded those skilled in the art.